PDL Emulator

High speed fiber optic transceivers, including those deploying coherent detection technology for 40Gb/s and 100Gb/s data transmission, must meet stringent PDL tolerance specifications. In addition, the PDL tracking speed and response time of the PDL mitigation algorithm of a coherent detection receiver must be quantified.
The PDLE-101 is specially designed for such PDL-related tests. This PDL source/ emulator can generate individual PDL values between 0 dB and 20 dB, with a resolution of 0.1 dB for PDL tolerance testing. It can also generate variable PDL with user defined range, waveform, and speed for PDL tracking speed and recovery time tests. The instrument can be controlled via the front panel keypad or by remote control via USB, RS-232, GPIB, or Ethernet interfaces. The residual PMD of the unit is less than 0.1 ps.
PDL Tolerance Test
PDL Tracking Speed and Recovery Time Tests
Code Development for PDL Compensation

Key Features

• High Resolution
• Wide Range
• Low Residual PMD
• PDL Scanning

DGD 1000

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